P5 microarchitecture processors
Original Pentium
- Bus width 64 bits
- System bus clock rate 60 or 66 MHz
- Address bus 32 bits
- Addressable Memory 4 GB
- Virtual Memory 64 TB
- Superscalar architecture
- Runs on 5 volts
- Used in desktops
- 16 KB of L1 cache
- P5 – 0.8 µm process technology
- Introduced March 22, 1993
- Number of transistors 3.1 million
- Socket 4 273 pin PGA processor package
- Package dimensions 2.16" × 2.16"
- Family 5 model 1
- Variants
- 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
- 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
- P54 – 0.6 µm process technology
- Socket 5 296/320 pin PGA package
- Number of transistors 3.2 million
- Variants
- 75 MHz Introduced October 10, 1994
- 90, 100 MHz Introduced March 7, 1994
- P54CQS – 0.35 µm process technology
- Socket 5 296/320 pin PGA package
- Number of transistors 3.2 million
- Variants
- 120 MHz Introduced March 27, 1995
- P54CS – 0.35 µm process technology
[edit] Pentium with MMX Technology
- P55C – 0.35 µm process technology
- Introduced January 8, 1997
- Intel MMX (instruction set) support
- Socket 7 296/321 pin PGA (pin grid array) package
- 32 KB L1 cache
- Number of transistors 4.5 million
- System bus clock rate 66 MHz
- Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
- Variants
- 166, 200 MHz Introduced January 8, 1997
- 233 MHz Introduced June 2, 1997
- 133 MHz (Mobile)
- 166, 266 MHz (Mobile) Introduced January 12, 1998
- 200, 233 MHz (Mobile) Introduced September 8, 1997
- 300 MHz (Mobile) Introduced January 7, 1999
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